Jim Keller: Moore’s Law is Not Dead

Caption notes

In this Berkeley talk, Jim Keller discusses transistor density, clock frequency and memory latency separately because they change at different rates. He argues that even with more transistors available, architecture teams still have to decide where to spend them. In the Q&A, he gives the example of an L1 cache: increasing capacity can cost another cycle, so he describes distributing capacity across the cache hierarchy and considering more access ports.